Multi-cores / Many-cores 2007
55 Fourth Street, San Francisco, California 94103 USA www.marriott.com/property/propertypage/SFODT
8:25 AM - 5:30 PM
Abstract
Many-core computing systems composed of low-power multi-core processors will soon be a commercial reality. These scalable systems will provide both a new capability and a challenge with respect to their practical application. Today, several vendors are designing high performance low power chips containing thousands of parallel processing elements. The effective utilization of these massively distributed systems on a chip and their aggregate computing systems will be the litmus test of the practical utility of these new class of architectures.
With the recently announced NSF Petascale acquisition effort, the phase three DARPA HPCS effort and emerging commodity architectures like the STI CELL architecture, the Sun Niagra / Rock architectures in addition to architectures from Intel and AMD, there has been a plethora of activity in multi-core programming models. The objective of Multi-cores / Many-cores 2007 is to take a holistic look at how these new scalable systems can be utilized, and the technical issues involved in programming applications for these systems.