Sponsored by:

Language Runtimes '04
Impact of Next Generation Processor Architectures On Virtual Machines

Organizer:
Yahya H. Mirza Aurora Borealis Software yahya@aurorasoft.net
Advisory Committee:	Program Chair:
Frederica Darema NSF fdarema@nsf.gov	Ralph E. Johnson UIUC johnson@cs.uiuc.edu
Program Committee:
Aart Bik Intel Corporation aart.bik@intel.com	Richard Lethin Reservoir Labs, Inc. lethin@reservoir.com
George Bosworth Microsoft "Retired" georgebosworth@acm.org	Timothy G. Mattson Intel Corporation timothy.g.mattson@intel.com
Tarek El-Ghazawi George Washington Univ. tarek@gwu.edu	Mark Mendell IBM Toronto Laboratory mendell@ca.ibm.com
Mootaz Elnozahy IBM Austin Research Labs mootaz@us.ibm.com	Kevin K. O'Brien IBM T. J. Watson Labs caomhin@us.ibm.com
Alexander Garthwaite Sun Microsystems Labs alex.garthwaite@sun.com	David Padua UIUC padua@uiuc.edu
Vinod Grover Microsoft Corporation vinodgro@microsoft.com	Christopher Vick Sun Microsystems Labs Christopher.Vick@Sun.COM

Important Information:
Date:
Thursday, October 28, 2004 8:30 - 5:00 Full Day
Location:
Vancouver Convention and Exhibition Centre Vancouver British Columbia Canada
Themes and Goals:
The objective of this workshop is to discuss and possibly come to a consensus on what technical issues need to be considered to fully leverage the next generation of processor architectures by future virtual machines and advanced language architectures. While the problem domain is restricted to addressing virtual machine, runtime, and language issues, experience reports from researchers building parallelization / vectorization solutions for alternative systems including but not limited to OpenMP, MPI, PVM, or parallel solutions targeting existing virtual machines including JVM, Squeak VM, .NET CLI, or other virtual machine architectures are also welcome. Specific topics of interest for our workshop include: Applications perspective for leveraging next generation processor architectures. New languages, constructs, and programming models to leverage parallel hardware resources. Programming models unifying local, in-process, and remote communication. Next generation compiler infrastructures for optimizing JIT compilers. Automatic parallelization and vectorization techniques for JIT compilers. Techniques to expose data-level parallelism to applications via the VM execution model. Techniques for converting data / loop-level parallelism into thread-level parallelism. Practical applications of profile guided ptimizations for parallel computing. Integration of OO programming with data and thread-level parallelism programming models. Impact of fine-grained thread models enabled by multi-core processors on SPMD languages. Techniques for dynamic load balancing of computations between processing elements. Optimizations for reduced power consumption.